A Multiple Interpolation Algorithm to Improve Resampling Accuracy in Data Triggers

نویسندگان

چکیده

To address the problem of low trigger accuracy during resampling and variable sampling rate using a fixed analog-to-digital converter (ADC), this paper proposes an interpolation method combining sinc linear to improve accuracy, based on digital trigger. After behavior simulation verification actual field programmable gate array (FPGA) test verification, data collected by two 3GSps 12-bit ADCs were subjected 8-times followed 16-times processing, after which original was increased 128 times could be realized vary between 100 MHz 1 GHz. A signal–noise ratio (SNR) 46.80 dBFS, spurious free dynamic range (SFDR) 45.91 dB, effective number bits (ENOB) 7.48 obtained direct without algorithm processing in simulation. Meanwhile, SNR 58.98 SFDR 60.96 ENOB 9.42 processing. Due influence analog link signal loss interference development board, SNR, 51.97 61.26 8.32 bits, respectively, from FPGA test. The experimental results show that has not only improved triggering but also SFDR, parameters.

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ژورنال

عنوان ژورنال: Electronics

سال: 2023

ISSN: ['2079-9292']

DOI: https://doi.org/10.3390/electronics12061291